The MAC, the PHY and their wires

Two chips, two jobs

An Ethernet interface is two parts. The MAC deals in frames: it builds them with their addresses and CRC, checks the CRC on the way in, and drops frames not meant for this station. The PHY deals in the cable: it turns bits into signals on the pairs and back, and runs the link, auto-negotiation included. That is the beginner's split; the exact line varies by chip.

On the classic ESP32 and the ESP32-P4 the MAC is inside the chip and the PHY is a separate part, joined to it by traces on the board.

Seven signals and a clock

RMII, the reduced media independent interface, joins them with seven signals. TXD0, TXD1 and TX_EN, two data lines and a transmit enable, run from the MAC to the PHY. RXD0, RXD1 and CRS_DV, carrier sense and data valid, come back. The seventh is REF_CLK, a continuous 50 MHz clock. Each tick moves two bits in each direction, so a byte takes four ticks.

Every data line is read against that clock, so the design must say who makes it: the PHY from its crystal, an oscillator, or the MAC. Both chips must be set up to agree. If neither drives it, no bit crosses.

The management bus

Two more wires, MDC and MDIO, are the management interface of clause 22 of IEEE 802.3: MDC the clock, MDIO the data. Over them the MAC reads and writes the PHY's registers. Some control speed and auto-negotiation; a status register reports whether the link is up, and ESP-IDF's driver reads it to raise a link-up event.

Several PHYs can share one management bus, so each answers to its own address. Ask at another address and nobody answers: to the driver, there is no PHY.

Seven RMII signals and the two management wires make nine. The full MII needs up to eighteen.

Lesson 8 follows a frame up to an IP address. For a real board's wiring, see Ethernet instead of Wi-Fi in the ESP32 book.

Common mistakes

• Expecting the PHY to deal in addresses. In the usual split the MAC handles frames and their addresses; the PHY handles signals and the link.
• Leaving the clock source to chance. Any of three can make REF_CLK, but both chips must be set up for the same one.
• Asking at the wrong PHY address. A PHY answers only to its own address, so the driver's setting must match the board.