SPI/Wider belts/Quad SPI
Lesson 12 of 14 · in 3D and VR

Quad SPI

Quad SPI turns four pins into four data lines pointing the same way, so a byte takes two clocks instead of eight. It costs the two-way swap, and it costs a short silence between the address and the data.

Lonely BinaryUpdated 2026-09-304 min readNo board required

View it in VR

Lesson 12 of the SPI course opens in a VR headset, on a table in front of you, and a voice starts three seconds after you arrive. Type this short address into the browser on a headset such as Meta Quest or Apple Vision Pro, and press Enter VR. No headset? Press Start the lesson: the same lesson, full screen.

learn.lonelybinary.com/vr/spi/12

The two extra lines come from pins that already exist. A Winbond W25Q128JV flash chip has a write-protect pin and a hold pin. Its datasheet says that when a status bit called Quad Enable is set, /WP becomes IO2 and /HOLD becomes IO3. With IO0 and IO1, the old DI and DO, that is four data lines, and a byte crosses in two clocks.

One way at a time

A quad read is half-duplex. The controller sends its command, every line turns round, and the chip drives all four. Nothing goes the other way, so the swap of ordinary SPI is gone.

That suits memory, which is all talk from one side. It is how a chip reads its flash and PSRAM, and how some display controllers are driven. It is no use to a sensor that answers a byte with a byte.

Where the four lines start

Each command decides for itself. Fast Read Quad Output, 0x6B, sends the instruction and the 24-bit address on IO0 alone, and only the data comes back on four lines. Fast Read Quad I/O, 0xEB, sends the instruction on IO0 and then the address on all four. esptool calls these modes QOUT and QIO. The plain read, 0x03, is single-line only.

The silence

Between the address and the data sit dummy clocks. The 0x6B read has eight. The 0xEB read has two mode clocks and four dummy clocks. On the datasheet's timing diagram the pins switch from input to output there, and no line carries data in between.

Reading four bytes with 0x03 takes 64 clocks: 8 for the command, 24 for the address, 32 for the data. With 0x6B it takes 48, and with 0xEB it takes 28. Quad pays when the read is long enough to outweigh the wait.

Common mistakes

  • Forgetting Quad Enable. It is a status bit. Some ordering options of the chip ship with it set and others without, so a quad read can fail on one board and work on its twin.
  • Leaving WP and HOLD wired for their old jobs. In quad mode they are data lines. esptool says QIO needs them wired to the chip's IO2 and IO3, and falls back to DIO if they are not.
  • Expecting four times the speed. The command still goes on one line, and the dummy clocks are dead time.

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