UART/One byte on one wire/Idle high, then a start bit
Lesson 2 of 12 · in 3D and VR

Idle high, then a start bit

A UART line rests high, and a byte begins when it falls for one beat, the start bit. That fall is the only warning the receiver gets, and it starts the receiver's own timer.

Lonely BinaryUpdated 2026-10-014 min readNo board required

View it in VR

Lesson 2 of the UART course opens in a VR headset, on a table in front of you, and a voice starts three seconds after you arrive. Type this short address into the browser on a headset such as Meta Quest or Apple Vision Pro, and press Enter VR. No headset? Press Start the lesson: the same lesson, full screen.

learn.lonelybinary.com/vr/uart/2

The line rests high

When a UART has nothing to send, its TX pin sits at the high level. That resting state is called idle, and it is the level the line returns to between frames. The ESP32 manual puts the two ends of a frame plainly: the start bit is logic low and the stop bits are logic high.

Idle is a state of the line, not a time. Nothing in UART says how long a line must rest between two bytes. A byte can follow the previous one immediately, or an hour later.

One low beat

A frame begins when the line falls from high to low and stays low for one beat. That is the start bit. It carries no data. Its whole job is to be a change the receiver cannot miss.

It has to be a fall because a byte can start with ones. A byte of all ones, 0xFF, puts the line high for all eight data bits, and a resting line is high too. Without a start bit that goes low first, the receiver could not tell a byte of ones from silence.

The receiver's own timer

There is no clock wire, so the receiver has to make its own sense of time. It does that from the fall. On the falling edge it resets its counters and starts counting beats at the speed both ends agreed. Maxim's application note on UART timing describes it this way: the receiver restarts its count on the falling edge and expects the middle of the start bit a half beat later.

Lesson 6 follows that timer through a frame.

What it costs

A receiver that joins a stream halfway has no way to know it came in late. Data bits fall to low as well, so the first fall it sees may be inside a byte, and it can take that for a start bit. It reads nonsense until the line rests long enough for the next real start bit to be the first fall it meets. That is one reason the first byte after plugging in a cable, or after resetting one side, can be wrong while the ones after it are right.

The ESP32 book goes through the whole frame on a real board in UART, start to stop.

Common mistakes

  • Thinking the start bit is the first bit of the byte. It is not part of the byte. The first data bit comes after it.
  • Blaming the cable for one bad byte after reconnecting. The receiver probably came in mid-frame and found a false start. Send something again and see.
  • Treating an unplugged RX pin as idle. An input with nothing connected floats and reads whatever it picks up. Idle high means somebody is driving the line high.

Edit this page — content/fundamentals/uart/idle-and-start.mdx

Discuss this article

Ask about this page. The answer stays here, on the page it belongs to, for whoever hits the same wall next.

Browse Fundamentals on the forum →