UART/Timing and trouble/When the settings disagree
Lesson 7 of 12 · in 3D and VR

When the settings disagree

A UART has no clock wire, so the only thing that makes two devices agree is a set of settings each keeps for itself. When they differ, nothing on the line says so. The receiver reads the wrong bits, and the usual evidence is wrong bytes.

Lonely BinaryUpdated 2026-10-015 min readNo board required

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Lesson 7 of the UART course opens in a VR headset, on a table in front of you, and a voice starts three seconds after you arrive. Type this short address into the browser on a headset such as Meta Quest or Apple Vision Pro, and press Enter VR. No headset? Press Start the lesson: the same lesson, full screen.

learn.lonelybinary.com/vr/uart/7

A UART receiver is told four things in advance: the baud, the number of data bits, the parity and the number of stop bits. Nothing on the line repeats them. The receiver starts a timer on the falling edge of the start bit and, from then on, takes its readings by counting its own beats. If its count of the frame differs from the sender's, it reads the frame wrongly, and it has no way to find out.

A clock that is a little off

Take two devices that agree on 9600 baud and 8N1, where the receiver's beat is a few percent longer. Each reading lands a little later in its bit than the one before it, and the lateness adds up across the frame. The first data bit is read almost in the middle of its beat. The stop bit is read nine and a half beats after the edge, so it carries nine and a half beats of accumulated error.

That is why the stop bit goes wrong first. When the reading slides half a beat, it lands on the edge of the bit and then in the next one. Half a beat spread over nine and a half beats is about 5 %. That figure is arithmetic for the difference between the two clocks, with perfect edges and no noise. It is a ceiling, not a safe setting. Designers aim lower, around 2 % to 3 % of total mismatch, to leave room for slow edges and for both clocks being a little off. The figure depends on the clocks and on the frame: a parity bit makes the frame one beat longer and the ceiling a little lower.

The error does not accumulate beyond one frame. The next start bit starts the receiver's timer again, so a stream of frames is as good or as bad as a single one.

A setting that is wrong

A baud that is far off, such as half or double, makes the receiver count the frame in beats of the wrong length, so its readings land in the wrong bits from the second one on. A different number of data bits makes the receiver stop counting too early or too late. It takes a data bit for the stop bit, or the start of the next frame for a data bit. Parity and stop bits do the same.

What you see depends on the data. A receiver can raise a framing error, which is a low where the stop bit should be high, and it can also deliver the wrong byte with no flag at all. Lesson 9 returns to that.

What it costs

A mismatch is quiet. Nothing is damaged and no error is printed, which is why a wrong setting is easy to mistake for a bad wire, a bad board or a bad driver. The cure is to read the settings off both datasheets and to set all four, as a set, to the same values on both ends.

Common mistakes

  • Treating 5 % as the safe tolerance. It is the ceiling for an 8N1 frame under ideal conditions. Real links should stay well inside it.
  • Matching the baud and forgetting the frame. 9600 8N1 and 9600 7E1 are different settings, and the line carries neither name.
  • Reading wrong bytes as a broken wire. A bad wire is one cause, and a wrong setting is another. The settings cost nothing to check, so check them first.

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