Sampling in the middle

Both ends know how long a beat is. That is not enough to read a byte, because the receiver also has to know when. Nothing on the wire says where a beat begins, except one thing: the line falling from idle to the start bit.

The edge starts the timer

The receiver waits with the line high. When it sees the falling edge, it starts counting from its own clock and expects the middle of the start bit half a beat later. It looks at the line there once more, to check it is still low; if it is high again, the edge was a noise spike and the receiver goes back to waiting. Then it looks once per beat, one beat apart, and writes down the level at that instant: first the data bits, then parity if there is one, then the stop bit.

What the line does between those looks is never read, as long as it has settled by the moment of a look.

Why the middle

The edges of a beat are where the line changes, and where a late edge or a bit of noise does its harm. The middle is as far from both edges as a look can be, so it has the most room to be early or late on either side. Clocks that disagree move the looks away from the middle, and the byte reads right until a look crosses an edge.

Counting ticks

Many UARTs get the middle by counting. A fast clock inside runs at sixteen times the baud rate, so each beat is sixteen ticks, and the receiver looks on tick eight after the edge and every sixteen ticks after that. Some parts take three looks around the middle and go with the majority. Sixteen is a common design, not a rule: other receivers count eight or four, and the ESP32's reference manuals do not say what the chip does, only that its receiver detects the start bit and then stores the data bits.

Every start bit starts again

The timer is set on each start edge, so each frame is read on its own. A receiver whose beat is a little long drifts to the right through a frame, and the last look, on the stop bit, is the furthest from the middle. Then the next start bit sets it back to zero. A difference between two clocks is therefore a problem within one frame and never across a long stream.

What it costs

The room is finite, and the last look is the one that uses most of it, because the error has had the whole frame to add up. If the two clocks disagree enough, a look crosses an edge and the byte reads wrong. How much is enough depends on both clocks and on the frame, and the next lesson works it out.

Common mistakes

• Thinking the receiver watches the whole beat. It looks at one instant per beat.
• Thinking sixteen ticks is how every UART works. It is one common design. Say so, and do not claim it for a chip whose manual does not.
• Thinking error builds up over a long stream. It builds up inside a frame and is cleared by the next start bit.