logic analyzer/Turning edges back into bytes/11. When the decode is wrong
Turning edges back into bytes · 11 of 11

When the decode is wrong

A decoder handed the wrong two channels does not report an error. It reports bytes — plausible addresses, plausible acknowledgements, a plausible failure to respond — and there is nothing on screen to say any of it is fiction.

The failure mode worth naming

A protocol decoder is a pattern matcher. Give it two channels and tell it which is which, and it will find start conditions, group bits into bytes and report them — and it will do that whether or not the two channels are the ones you meant.

There is no error state for "these are the wrong wires". The output looks like output.

A decode that runs and is wrong
SCL and SDA as wired
What the decoder was told
Decoder errors shown
0
Bytes reported
1
Bytes that are real
1
The clock is the row with even pulses and nothing else. That is the shape to check before you trust anything below it: SCL is a metronome, SDA changes only while SCL is low, and the two never look alike on a real bus.

The tell is in the trace, not in the bytes

You cannot spot a swapped pair by looking at the decoded row, because the addresses it produces are in range and the acknowledgements are plausible. You spot it one row up.

A clock is a metronome. On a real bus SCL is an even run of pulses with regular spacing, and SDA changes only while SCL is low. So if the row you have called the clock has long stretches with no edges in them, or changes level at moments the other row is also changing, it is not a clock.

That check takes two seconds and it is the first thing to do when a decode looks odd. Swapping two channel numbers in the decoder settings is far cheaper than re-clipping anything.

The three things that produce a wrong decode

The wrong channels. Covered above. The most expensive of the three, because it is the only one that produces confident, wrong output.

Too few samples per bit. The arithmetic chapter predicts this before you capture. Below about four samples a bit the decoder is not reading your traffic; it is finding patterns in an undersampled approximation of it, and reporting runs of 0x00 and 0xFF is what that usually looks like.

A gap in the stream. Dropped samples do not stop a capture. They leave a shorter transaction behind, and a shorter transaction is still a valid one as far as the decoder is concerned. A decode that works for the first half of a capture and disintegrates in the second is this, almost every time.

Notice that only the first is about wiring. The other two are settings you chose before pressing capture, which is the argument for reading the two chapters that cover them before the session rather than after it.

Failures that are honest

Not everything fails quietly, and it is worth knowing which ones announce themselves so you can be glad to see them.

  • Both clips on the same wire gives the decoder two identical rows, no start condition, and an empty result. That is an unambiguous message.
  • A completely dead bus gives two flat lines. Also unambiguous.
  • SPI with the wrong clock phase shifts every byte by a bit, which reads as garbage rather than as data — obvious enough to chase.

The quiet ones are a swapped pair, an undersampled bus and a dropped sample. Those three are the reason to check the trace before trusting the row under it.

Working up the stack

When a stacked decoder — an I²C device decoder sitting on an I²C decoder — says something impossible, work upward rather than downward.

Only the top row came off the wire. Everything below it is software reading the row above using settings you supplied, so a nonsense register name at the bottom is nearly always a wrong channel or a wrong chip selection somewhere above it. Check the raw traces have edges, then the protocol decoder, then whatever is stacked on it. The silicon is the last suspect, not the first.

When it does not work

The decoder reports an address that is close to mine but not mine

Suspect the channel assignment before the sensor. Swapping SDA and SCL in the decoder settings produces a different, entirely in-range address from the same capture, with no warning. Look at the row you called the clock: SCL is an even run of pulses, and a clock that sits still for three bit times is a data line.

Every byte comes back as 0x00 or 0xFF

Usually too few samples per bit rather than a wiring fault. The decoder is landing on the same level repeatedly and grouping it into bytes. Divide the sample rate by the bus clock, and if the answer is under about four, slow the bus down for the debugging session.

The decode is right for a while and then falls apart

A gap in the stream. At high sample rates the USB bus drops samples without stopping the capture, and a missing microsecond leaves a shorter, plausible transaction behind. Lower the rate, move off the hub, and try again — if the decode survives, that was it.

SPI decodes but the bytes are shifted by one bit

The clock polarity or phase in the decoder settings does not match the bus. Both applications let you choose which edge the data is sampled on, and picking the wrong one shifts everything by half a clock. Try the other setting before you suspect the device — it costs one click.

Two channels are identical and I wired two different pins

Check what the clips are physically on. On the expansion board the clip pads run CLK, GND, 7, 5, 3, 1, 6, 4, 2, 0 rather than in numerical order, so two clips a pad apart are not two adjacent channels. It is also what a genuine short looks like, which is worth ruling in as well as out.

Where this goes next

You can now see what is on the bus. The next question is what should be, and why two sensors from the same family will not share it.

Addresses, and what to do when two devices claim one

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