LVDS

A GPIO on an RGB bus swings between ground and the supply. An LVDS transmitter does something else. A typical one drives about 3.5 mA through a 100 Ω termination at the receiver, which is roughly 350 mV across the pair. The receiver compares the two wires, so noise that moves both together is largely ignored.

Seven bits on a pair

LVDS also serialises. In the 7:1 scheme used for laptop panels, each data pair carries seven bits in one pixel-clock period, and the clock gets its own pair. A common 18-bit panel uses three data pairs plus one clock pair. A 24-bit panel adds a fourth data pair: four plus one.

The mapping of the fourth pair is not universal. JEIDA and VESA put bits of different significance on it. The wrong choice leaves the picture intact and the colours wrong.

A bridge, not a wire

An RGB-to-LVDS transmitter such as the TI SN75LVDS83B takes parallel data and a pixel clock and serialises them onto the pairs. You cannot do that in wiring, because it is voltage levels and timing, not only order.

The bridge is not memory. This class of panel has no frame store and needs the pixel stream to keep coming. Stop the RGB input and the LVDS stream stops with it.

On the ESP32

No ESP32 outputs a laptop-panel LVDS link directly. With an ESP32-S3 in a 16-bit RGB565 configuration, the bridge receives the MCU's bit mapping and converts it to the panel's LVDS mapping. The input width and bit order must match on both sides. A bridge helps only if the MCU can supply an interface the bridge accepts.

Common mistakes

• Treating LVDS as digital RGB on other wires. It is a different signalling standard. Changing the wire order does not make a GPIO into a differential driver.
• Ignoring JEIDA and VESA. A 24-bit panel on the wrong mapping shows a recognisable picture in wrong colours.
• Expecting a bridge to hold the picture. It translates the signal and does not store it. A panel of this class needs its continuous stream.