Screens/Fast links/MIPI DSI lanes
Lesson 12 of 16 · in 3D and VR

MIPI DSI lanes

Few wires do not mean little bandwidth. A DSI lane is a differential pair running at up to gigabits a second, and lane count, per-lane rate, signalling state and timing together decide whether a panel's mode fits.

Lonely BinaryUpdated 2026-10-014 min readNo board required

View it in VR

Lesson 12 of the Screens course opens in a VR headset, on a table in front of you, and a voice starts three seconds after you arrive. Type this short address into the browser on a headset such as Meta Quest or Apple Vision Pro, and press Enter VR. No headset? Press Start the lesson: the same lesson, full screen.

learn.lonelybinary.com/vr/screens/12

A D-PHY data lane is two wires that carry one signal. The receiver reads the voltage difference between them. Interference that lifts both wires together leaves that difference almost unchanged, which is why a thin flat cable can carry a fast signal.

Add lanes and the same per-lane rate gives more in total. Four lanes at a given rate have twice the raw capacity of two lanes at that rate.

Two electrical states

A lane is not always fast. It idles in a low-power state called LP-11, bursts in high-speed mode while pixels cross, and returns to LP-11 afterwards. Those states are why a lane's voltage swings look different before and during a burst.

The arithmetic

Take a 1024 × 600 panel in RGB888, as our bench does. The active pixels alone are a payload figure of 442.4 Mbps at 30 Hz and 884.7 Mbps at 60 Hz. With our example blanking the total is about 615 Mbps at 30 Hz and about 1.23 Gbps at 60 Hz. Across two lanes that is about 307 and about 614 Mbps per lane, before any protocol overhead.

These are teaching figures for one timing example. A real panel states its own timing, and overhead is on top.

So a panel that works at 30 Hz and fails at 60 Hz can be short of link rate or timing margin. That is a hypothesis to test, not a diagnosis.

On the ESP32

Only the ESP32-P4 has a DSI host. It provides two data lanes rated at 1.5 Gbps each, so 3.0 Gbps of rated lane capacity. The ESP32-S3 and the classic ESP32 have no native DSI. A longer treatment of driving one is in MIPI displays on the ESP32.

Common mistakes

  • Reading wire count as bandwidth. A few pairs at gigabits each can carry more than a wide parallel bus at megahertz. Count lanes and rate.
  • Expecting a cable to fail on wire count. Common-mode noise lifts both wires and leaves the difference alone. A link is more likely to be limited by its rate or timing margin, and that is a hypothesis to test.
  • Comparing a payload figure with a link rating. The 1.5 Gbps is per lane and rated. The 884.7 Mbps is active pixels alone. Blanking and overhead come on top of it before you compare.

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