Screens/Screens with their own memory/SPI TFT
Lesson 4 of 16 · in 3D and VR

SPI TFT

A TFT controller does not know where a pixel belongs until you open a window. CASET and RASET set the rectangle, RAMWR pours pixels into it, and two byte-order mistakes can ruin the colours.

Lonely BinaryUpdated 2026-10-014 min readNo board required

View it in VR

Lesson 4 of the Screens course opens in a VR headset, on a table in front of you, and a voice starts three seconds after you arrive. Type this short address into the browser on a headset such as Meta Quest or Apple Vision Pro, and press Enter VR. No headset? Press Start the lesson: the same lesson, full screen.

learn.lonelybinary.com/vr/screens/4

SCLK, MOSI and chip select work as in the SPI course. Our TK89 kit uses the ST7789, ST7735 and ST7796 families, and the timing bench here uses an ST7789VW example.

Initialise, then address

The controller needs a start-up command sequence before drawing can be trusted. After that, one extra pin matters. D/C tells the controller whether the byte on MOSI is a command or display data.

To draw, set a window. Column Address Set, CASET, gives the left and right edges. Row Address Set, RASET, gives the top and bottom. Memory Write, RAMWR, then sends pixels that fill exactly that rectangle. A small change stays a small transfer instead of 153,600 bytes.

Some smaller ST7789 panels, such as 240 × 240 or 135 × 240, use only part of the controller's RAM. The visible glass then starts at an X or Y offset that changes with rotation, and a window at coordinate zero lands in the wrong place.

Colour, byte order, and speed

Every RGB565 pixel arrives as two bytes. If they arrive in the wrong order, correct colours turn to nonsense. A separate colour-order setting swaps red and blue when the controller expects BGR and the data is RGB.

For a 240 × 320 frame the payload alone takes 122.9 ms at 10 MHz, the ILI9341 datasheet reference. It takes 30.7 ms at 40 MHz, a common practical setting, 19.7 ms at 62.5 MHz, the ST7789VW's 16 ns write cycle, and 15.4 ms at 80 MHz. Forty and eighty are host settings, not panel promises. Commands, DMA and software decide what you achieve, and 80 MHz does not guarantee 60 frames per second.

The ESP32 SPI page covers the pins and the clock limits, and the whole family can drive an SPI TFT.

Common mistakes

  • SPI knows where the pixels go. It only moves bytes. The window from CASET and RASET is what places them, and some panels need an offset on top.
  • Wrong colours mean a broken panel. Usually the two bytes of each pixel are swapped, or red and blue are, and a setting fixes it.
  • The fastest host clock is the display's speed. 80 MHz is an ESP32 setting. The panel, the commands and the DMA chain set the real rate.

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