Sixteen bits and a latch
Every instruction the chip takes is one sixteen-bit message: CS goes low, sixteen bits go in on DIN, one per rising edge of CLK, and CS goes high again. Nothing on the display changes until that last rising edge.
One message
A message is two bytes. The first byte's low four bits are the register's address; its top four are ignored. The second byte is what goes into the register. So 0x0C then 0x01 wakes the chip, 0x0A then 0x04 sets brightness 4, and 0x03 then a byte fills column 3.
The three wires each have one job. DIN carries the bit. CLK says when to read it: the chip reads DIN on each rising edge. CS frames the message: it goes low before the first bit and high after the sixteenth, and the rising edge of CS is the moment the register takes the new value. The datasheet's name for that pin is LOAD, which describes it better.
The five messages every sketch sends
After power-up the chip is asleep, scanning one column at minimum brightness with its display blank. So a sketch sends five messages before its first picture, and the book's sketch sends them in this order:
| Register | Value | What it does |
|---|---|---|
| 0x0F | 0 | display test off |
| 0x09 | 0 | no decoding: every bit is one LED |
| 0x0B | 7 | scan all eight columns |
| 0x0A | 4 | brightness 4 of 15 |
| 0x0C | 1 | wake up |
Leave out the last one and nothing lights, with no error anywhere. Leave out the third and only one column ever lights.
In the sketch
The book's send() is four lines: CS low, shiftOut the address byte,
shiftOut the data byte, CS high. shiftOut with MSBFIRST sets DIN and
pulses CLK eight times, top bit first, which is the order the chip expects.
When it does not work
Bits are arriving in the wrong place: DIN and CLK swapped, a loose wire, or a message one bit short. Count from GND: DIN is the fourth pin and CLK the sixth, with NC between them. Then check each message is exactly sixteen bits.
Only at the top. The chip takes up to 10 MHz, a clock period of 100 ns. The book's sketch uses shiftOut and a MicroPython loop, both far slower than that, which is fine: the chip keeps no time of its own on DIN and CLK.
No. The MAX7219 only listens. Its one output, DOUT, repeats what came in on DIN sixteen and a half clocks later, and on the TK52 even that reaches no pad.
Near enough that the SPI hardware of any board can send it: data changes while the clock is low and is read on the rising edge, top bit first. CS on this chip is really a latch, LOAD, and the message takes effect when it rises.
The supply and the signals, and why they follow different rules.
5 V on VCC, 3.5 V for a HIGH →Edit this page — content/books/matrix-led/sixteen-bits-and-a-latch.mdx
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